Signal Name Total Product Terms Product Terms Location Pin Number PinType Pin Use GCK
data<8> 3  UCT2 0 1 MC1 168 I/O I/O  
(unused) 0   MC2   (b)    
chip_sel<5> 0   MC3 169 I/O O  
(unused) 0   MC4   (b)    
(unused) 0   MC5   (b)    
(unused) 0   MC6   (b)    
(unused) 0   MC7   (b)    
(unused) 0   MC8   (b)    
(unused) 0   MC9   (b)    
(unused) 0   MC10   (b)    
(unused) 0   MC11   (b)    
SAN_BUFR 4  UCT4 4 5 6 MC12   (b) (b)  
chip_sel<6> 0   MC13 170 I/O O  
chip_sel<3> 0   MC14 171 I/O O  
col_clk_BUFR 4  UCT4 2 3 4 MC15   (b) (b)  
chip_sel<4> 0   MC16 172 I/O O  

Signals Used By Logic in Function Block
  1. CLK
  2. FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE
  3. FSM/SHELL1_DSP_SM_2/CHIP_IDLE
  4. FSM/SHELL1_DSP_SM_2/CHIP_INIT
  5. FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS
  6. FSM/SHELL1_DSP_SM_2/CHIP_READ2
  7. FSM/SHELL1_DSP_SM_2/CHIP_READ3
  8. FSM/SHELL1_DSP_SM_2/CHIP_READ4
  9. FSM/SHELL1_DSP_SM_2/CHIP_READ_0
  10. FSM/SHELL1_DSP_SM_2/CHIP_READ_5
  11. FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0
  12. FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1
  13. FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT
  14. FSM/SHELL1_DSP_SM_2/CLR_0
  15. FSM/SHELL1_DSP_SM_2/CLR_0_1
  16. FSM/SHELL1_DSP_SM_2/CLR_1
  17. FSM/SHELL1_DSP_SM_2/CLR_1_1
  18. FSM/SHELL1_DSP_SM_2/CLR_2_1
  19. FSM/SHELL1_DSP_SM_2/PRE_RAMP
  20. FSM/SHELL1_DSP_SM_2/PRE_READ
  21. FSM/SHELL1_DSP_SM_2/PRE_READ_1
  22. FSM/SHELL1_DSP_SM_2/RAMP_S0
  23. FSM/SHELL1_DSP_SM_2/RAMP_S1
  24. FSM/SHELL1_DSP_SM_2/RAMP_S2
  25. FSM/SHELL1_DSP_SM_2/RAMP_S3
  26. FSM/SHELL1_DSP_SM_2/XMIT_END
  27. FSM/SHELL1_DSP_SM_2/XMIT_SLEEP
  28. FSM/SHELL1_DSP_SM_2/_n014252
  29. FSM/SHELL1_DSP_SM_2/chip_read_5_1
  30. N_PZ_1119
  31. N_PZ_849
  32. N_PZ_855
  33. SAN_BUFR
  34. cntr_cnt<0>
  35. cntr_sel
  36. cntr_set_value<0>
  37. col_clk_BUFR